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Photolink- Fiber Optic Receiver
PLR233 Series
Application Notes: PLR233 Series PCB layout for motherboard integration
To achieve better jitter and low input optical power performances, several PCB layout guidelines must be followed.
These guidelines ensure the most reliable PLR233 SERIESPOF performance for the motherboard integration. Failed to
implement these PCB guidelines may affect the PLR231 jitter and low input power performances.
1. Careful decoupling of the power supplies is very important. Place a 0.1uf surface mount (size 805 or smaller) capacitor
as close as (less than 2cm) to the POF Vdd and Gnd leads. The 0.1uf act as a low impedance path to ground for any
stray high frequency transient noises.
2. To reduce the digital noises form the digital IC on the motherboard, the planar capacitance formed by an isolated Vcc
and Gnd planes is critical. The POF device must be mounted directly on these two planes to reduce the lead parasitic
inductance.
3. The isolated Vdd and Gnd planes must be connected to the main Vcc and Gnd (digital) planes at a single point using
ferrite beads. The beads are used to block the high frequency noises from the digital planes while still allowing the DC
connections between the planes
Revision Copyright ?
Release Date:2013-05-30 14:26:12.0
8
LifecyclePhase:
2010, Everlight All Rights Reserved. Release Date : MAY.29.2013. Issue No: DPL-0000036_Rev.2 www.everlight.com
Expired Period: Forever
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